module sys_init
(
	input wire sys_clk,
	input wire sys_rst_n,
	output reg init_done
);

reg [9:0] cnt;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		cnt <= 10'd0;
	else if (cnt < 10'd20)
		cnt <= cnt + 1'b1;
	else
		cnt <= cnt;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		init_done <= 1'b0;
	else if (cnt == 10'd9)
		init_done <= 1'b1;
	else
		init_done <= 1'b0;

endmodule